• Authors: Alejandro Calderón Mateos & Felix García Carballeira

• License: GPL v3.0

Laboratory 2: microprogramming a compact instruction set

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The main goal of this laboratory is to learn how to design an instruction set for a computer. The main knowledge to be practiced are microprogramming, assembly programming and information representation.

For the development of the laboratory, it is necessary to review the following concepts:

• The representation of integers, character strings, etc.
• The main aspects of the assembly language.
• The instruction format and addressing types.
• The operation of a processor, including the stages of execution, microprogramming, etc.

The student is going to use the WepSIM simulator to be able to exercise in an interactive way the concepts and knowledge indicated above.

This laboratory consists of 2 exercises that you can develop and test in WepSIM.

Exercise 1

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The company we are work with request you to design, implement and test a new instruction set similar to the RISC-V instruction set, using the WepSIM simulator. Instructions are listed in Table 1. The instructions will be encoded in 32 bits.

Table 1.- RISC-V-like instruction set
The notation used for the instructions is the following one:

• U32 refers to a 32-bit unsigned integer.
• U16 to a 16-bit unsigned integer.
• S16 to a 16-bit signed integer.
• S10 to a 10-bit signed integer value.
• RRE will be used to denote RISC-V general purpose registers, which in this 32-bit version are 32 registers of 32-bit each. BR will be used to refer to the Register File, and BR[RRE1] to indicate the contents of the RRE1 register. The integers stored in register are two complements 32 bits integers.
• MEMORY[R] refers to the contents of the memory position whose address is stored in the R register.

The values "S16/S10" indicate that sign extension must be made while in "U16" no sign extension is made (filled with leading zeros).

The following is the mapping between RISC-V registers and WepSIM registers. This association must be indicated in the register section of the microcode of the requested instructions.


Table 2.- RISC-V registers
Each registers has two names and when programming it is possible to use both x0 or zero, x1 or ra, etc.
For the main control registers:

• The stack pointer register (sp) is the R2 register in the WepSIM elementary processor.
• The status register is the SR register in the WepSIM processor.
• The PC registry is the program counter register.

WepSIM RT1, RT2, and RT3 registers are transparent to the assembler programmer.

In order to pass arguments to a subroutine in our RISC-V assembler, the a0... a7 registers will be used, and the a0 and a1 registers will be used to return results (one value in a0, and for two values a0 and a1). In the case of our RISC-V, passing more than eight arguments to a subroutine, from ninth to last of the arguments would be passed on the stack. Consider that a subroutine has to keep the value within registers s0... s11, sp, fp and ra between calls.

The results of this exercise are related to the design of the microcode (memory of laboratory) and the microcode itself (mc file for WepSIM). A valid implementation that minimizes the number of clock cycles will be assessed, briefly justifying in memory the design decisions that have been made to achieve this.

Exercise 2

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To test the instructions of the exercise 1 you can encode the programs that you deem appropriate. However, the company asks us to carry out a program in assembler (in order to make a demonstration) that uses the RISC-V instruction set requested in exercise 1.

The program to be encoded, using the RISC-V statements designed in the previous section, will have the same functionality as that of the following program written in high-level language:

int32 vector[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 } ;

int sumav ( int32 neltos, int32 *vector )
{
     int32 v0 = 0 ;
     for (int32 i=0; i<neltos; i++) {
            v0 = v0 + vector[i] ;
     }
     return v0 ;
}

int main ( int argc, char *argv[] )
{
     int32 ret = sumav(10, vector) ;
     exit(0) ;
}

This program has a sumav routine that receives two arguments: the number of elements of an integer vector and the start direction of that integer vector. The routine returns the sum of the numbers contained in the vector passed by argument. There is also a main routine that takes care of calling the sumav routine and ending the program. Note the registers used in the convention for argument passing on this RISC-V are described at the end of Exercise 1.

The results of this exercise must be indicated both, the part of the memory corresponding to this exercise and in the file associated with the requested functionality.


Click here for some help on this exercise...

Extra material

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Save a checkpoint with WepSIM

WepSIM allows you to save the entire working session into a single file. This session can include the requested microcode, the assembly code, the states at different execution points, and a recording of the work session. In this way it is more agile to continue the work or share that work among members of the laboratory group.

To do this you have to use what in the WepSIM simulator is called checkpoint. The following are the steps to save a checkpoint:

• In the run mode menu select the "Checkpoint" option.
• Enter the file name in the "File name:" field, then press the "Save" button to save the file.
• Check that the file has been saved correctly and contains everything ordered in the statement.